1. Field of the Invention
The present invention generally relates to methods for determining yields of circuit components in integrated circuit designs, and more particularly to a method of determining correlated fail distributions (e.g., memory read failures) in memory arrays having memory cells formed into groups which connect to a single peripheral logic element.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. Although great care is taken in the design and fabrication of integrated circuits, there is still a small percentage of electrical components that can fail for various reasons including process variations, defective designs or incomplete testing. Even if the percentage of failing components is very small, it may still equate to a significant number of absolute failures when considering components having a very large quantity of circuit elements. For example, an integrated circuit (IC) chip for a state-of-the-art random-access memory (RAM) array may have millions of memory cells (bits), plus additional peripheral logic for local or global evaluation. Furthermore, unlike logic circuitry, a single or a few failing memory cells can lead to significant yield loss.
Means have been devised to mitigate the effects of component failures, such as the provision of error-correcting circuits or redundant circuits which enable recovery for a limited number of fails. However, with designers aiming for less than one part-per-million fails in memory designs, it is increasingly important to be able to pre-characterize the failures taking into consideration the impact of process variation parameters on yield and design considerations. In the case of memory circuits, designers are particularly interested in process variation within the transistors of the memory cells.
This challenge is becoming more difficult as process technology scales to the deep-submicron regime. Process variation in the peripheral logic, namely local evaluation circuitry in case of SRAM or primary sense amp in case of eDRAM, becomes critical as well. One design consideration which affects memory array yield is the manner in which the memory cells are connected to the peripheral logic, which may be understood by reference to the basic examples of FIGS. 1A, 1B and 1C. FIG. 1A illustrates a memory array 1 in which each memory cell 2 is connected to its own sense amplifier 4, i.e., the memory cell grouping is 1:1. In the example under consideration memory array 1 has ten such memory groups, and a set of ten of these memory arrays are replicated for a total of one hundred memory cells. FIG. 1B illustrates a memory array 6 in which two memory cells 2 are connected to a single sense amplifier 4, i.e., the memory cell grouping is 2:1. Memory array 6 has five such memory groups, and a set of ten of these memory arrays are again replicated for a total of one hundred memory cells. FIG. 1C illustrates a memory array 8 in which ten memory cells 2 are connected to a single sense amplifier 4, i.e., the memory cell grouping is 10:1. Memory array 8 has one such memory group, and a set of ten of these memory arrays are again replicated for a total of one hundred memory cells. Each memory cell plus its associated sense amplifier is considered to be a memory unit.
Without loss of generality, the effect of memory cell grouping on memory unit failure distribution can be seen by comparing the mean and standard deviation for failures of these sets of the three memory arrays based on a 10% probability of sense amplifier failure (1 in 10). Assuming this failure probability, the mean number of memory cell read failures per memory array is the same for each set of ten memory arrays 1, 6, 8, namely, one failure per array on average. More generally, the expected number of failures will be the same for any memory grouping if the array is replicated enough. However, the standard deviations for the failures are different for the three memory groupings. For memory array 1 shown in FIG. 1A, the standard deviation is zero because the number of failures is the same for each memory array (one failure per array). For memory array 6 shown in FIG. 1B, the standard deviation is 1.05 because the number of failures for five of the arrays will be zero and the number of failures for the other five arrays will be two. For memory array 8 shown in FIG. 1B, the standard deviation is 3.16 because the number of failures for nine of the arrays will be zero and the number of failures for the tenth array will be ten. Different failure distributions can have a significant impact on design recommendations and overall circuit yield.
The foregoing analysis is overly simplified since there may be multiple conditions leading to failure of a sense amplifier, and the memory cells may similarly be subject to multiple failure conditions. Moreover, the failure conditions of the sense amplifiers and memory cells may not be independent, introducing further complexity. Numerous statistical estimation methodologies have been formulated to investigate the effects of memory cell groupings, including Gumbel distribution, bounded sample span, and count data, but each of these approaches has certain drawbacks and limitations.
A Gumbel distribution (“max distribution”) provides a bound on the yield by examining the maximum of a probability density function; see for example the article by Robert Houle entitled “Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times,” Custom Integrated Circuits Conference pp. 37-40 (September 2007). This approach relies on the worst-case expected cell failure per group, and so is a useful tool to establish early design stage upper bounds, but it can be unreasonably pessimistic. While the max distribution technique is straightforward for a single independent variable, identifying the worst-case in the presence of multiple dependent variables can require complex simulations that are inordinately expensive.
Bounded sample span is a heuristic technique which takes advantage of the fact that the number of memory cells is much larger than the number of sense amplifiers, meaning that the sense amplifier sample span for any given parameter is expected to be smaller than the span of the memory cell samples in terms of the standard deviation (σ). For example, there may be one million memory cells and 30,000 sense amplifiers in a memory array with the memory cell samples reaching up to 5σ, but the sense amplifier samples will be within a smaller span (95% confidence) reaching up to 4σ. The bounded sample span approach also does a good job of capturing the mean, but does not capture the nature of the variance since is pertains primarily to bounds and does not replicate the true system.
Count data is a form of statistical analysis wherein observed values are stored as whole numbers rather than, for example, binary data. Statistical treatments of count data are commonly represented by Poisson, binomial, or negative binomial distributions. This approach is based on the independent and identically distributed (IID) assumption wherein the mean and variance are equal (equidispersion). However, this assumption is often violated in real-life, i.e., underdispersion and overdispersion can occur, and this is particularly true with a grouping of many memory cells connected to a single peripheral logic element. To capture the overdispersion or under-dispersion it is necessary to model the standard deviation of the estimate as a function of the mean of the estimate. This model requires having the samples of the systems which can be very exhaustive and approximate, and is further used only when data is readily available as is the case with hardware data. Accordingly, count data also fails to provide a useful indication of failure variance associated with memory groupings.
In light of the foregoing, it would be desirable to devise an improved method of estimating correlated failure distributions for memory array designs having different groupings of memory cells, which could accurately characterize variances without introducing excessive computational requirements. It would be further advantageous if the method could easily generate a grouping-based probably of fail for a memory unit, which cannot be derived from conventional unit analysis.